The invention is directed to an improved approach for selecting the appropriate product of uncommitted logic to use to implement an electronic design.
A modern integrated circuit (IC) has a large number of electronic components that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many modern IC designs are in the form of application-specific integrated circuits (ASICs), which are ICs that are customized for a particular use, rather than intended for general-purpose use.
The process to create and design the ASIC is normally a very expensive, complicated, and time-consuming endeavor. To design the ASIC, a designer typically first creates high level behavior descriptions of the IC device using a high-level hardware design language, which is then translated into netlists of various levels of abstraction using a computer synthesis process. At the physical level, the IC designer may then need to use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. Many errors are inadvertently introduced into this process, at both the logical and physical design stages, and the process to correct these errors prior to tape-out could end up consuming a significant amount of time and expense.
In many cases, the expense of designing a custom ASIC is considered to be excessive if the number of units needed to be manufactured is relatively small. Moreover, there is often the need to configure an IC for test purposes, where the cost of creating a custom ASIC for testing is prohibitively expensive.
To address these issues, the electronics industry provides products containing uncommitted arrays of logic that can be configured to create customized circuits or custom logic arrays. For example, a gate array (GA) is a prefabricated silicon chip circuit in which transistors, devices, and/or standard gates (e.g., NAND/NOR gates) are placed at regular predefined positions on a wafer. Creation of a circuit with a specified function is accomplished by adding a final surface layer or layers of metal interconnects to the chips during the manufacturing process, which allows the final version of the chip to be customized by a customer.
A field programmable gate array (FPGA) is another type of an IC that includes an array of uncommitted gates which are designed to be configured by the customer or designer after manufacturing. FPGAs contain programmable logic components that allow the array elements to be wired or programmed together, without the need to fabricate the final surface layer of interconnects as required by the gate arrays.
The process to manufacture an electronic circuit can be immensely simplified by using one of these products, since the designer avoids the need of performing full physical design, verification, and manufacture of a custom IC. Instead, the physical platform provided by the GA or FPGA can simply be configured to interconnect the pre-manufactured gates into a custom connected pattern to implement the electronic design.
To use these types of products, an application circuit must be built on a product that has enough gates, wiring elements, I/O pins, and other necessary devices to implement the requirements of the expected electronic design. Since requirements vary among customers of these products, such products usually come in product families of standard sizes, with certain products having more available on-board gates and components and other products in the product family having less on-board gates components, where the smaller members of the family have less capacity but also being correspondingly less expensive. For example, a manufacturer may produce a line of different gate array or FPGA devices, with each product having a different gate count or number of memory components.
The difficulty for a customer of these products is to decide upon the specific product to employ to implement an electronic design. Using a device that has too few gates for the expected design will be fruitless, since it will not have sufficient capability to implement the electronic design. Using a product that has more gates than are needed for the design will be a waste because the customer will have purchased more capacity than is needed.
The conventional approach to this process is to manually make this selection and determination of the appropriate product to use to implement the electronic design. The manufacturer would distribute data sheets or other types of product description documents, which the customer would use to manually review in conjunction with the requirements of the electronic design. Alternatively, the customer could create a spreadsheet to hold data from the data sheets, which is again analyzed in a manual fashion to make the determination.
These manual approaches to product selection are fraught with possible errors and could consume an excessive amount of time. Moreover, the results achieved by such manual processes are often mere guesswork by the designer. To reduce the risk of selecting an inadequate product, this often causes the designer to select a product that has far more capacity than is ultimately needed at an obviously increased cost.
Therefore, there is a need for a more efficient approach to identify the specific product that is used to implement an electronic design, where the product includes an array of uncommitted gates.